1. Field of the Invention
The present invention relates to a booster circuit, particularly to a booster circuit having a feedback circuit section.
2. Description of Related Art
In recent years, power consumption of a display device such as a liquid crystal display device is getting lower. A booster circuit is often used as a power source for such a display device. Although a simple charge pump circuit that operates continuously exists, a power source having a higher efficiency and lower power consumption is used more frequently for a built-in power source of the display device. Because of this situation, a charge pump circuit that has a feedback circuit section and performs a booster operation depending on load and output variation has been increasingly used.
FIG. 1 and FIG. 2 are circuit diagrams showing a typical feedback-type booster circuit. The typical feedback-type booster circuit will be described below with reference to FIGS. 1 and 2.
As shown in FIGS. 1 and 2, the booster circuit has a charge pump 10, a feedback circuit section 20 and a logic circuit section 30. The charge pump 10 has a DC/DC converter 11, a booster capacitor (C1) 12 and an output capacitor (CL) 13. The DC/DC converter 11 has a voltage input section 111, a clock signal input section 113 and a booster voltage output section 112. The feedback circuit section 20 has a voltage dividing circuit section 24, a comparison circuit section 21 and a reference voltage source section 22. The voltage dividing circuit section 24 has a first fixed resistor (R1) 241, a voltage dividing node 240 and a second fixed resistor (R2) 242. The comparison circuit section 21 has a comparator 210. The reference voltage source section 22 has a reference voltage source 220. The logic circuit section 30 has an external clock signal input section 31.
The voltage input section 111 is connected to the DC/DC converter 11. The DC/DC converter 11 is further connected to an output section of the logic circuit section 30, both terminals of the booster capacitor 12 and the booster voltage output section 112. The booster voltage output section 112 is further connected to the output capacitor 13 and an input section of the feedback circuit section 20. The output capacitor 13 is also connected to a ground 19. An output section of the feedback circuit section 20 and the external clock signal input section 31 are connected to two input sections of the logic circuit section 30, respectively.
In the feedback circuit section 20, the input section is connected to the second fixed resistor 242 in the voltage dividing circuit section 24. The second fixed resistor 242 is also connected to the voltage dividing node 240 at the other end thereof. The voltage dividing node 240 is further connected to the first fixed resistor 241 and an inverted side input section of the comparator 210. The first fixed resistor 241 is also connected to a ground 249 at the other side thereof. The reference voltage source 220 is connected to a non-inverted side input section of the comparator 210. The reference voltage source 220 is also connected to a ground 229 at the other end thereof. An output section of the comparator 210 is connected to the output section of the feedback circuit section 20.
A basic operation of the DC/DC converter 11 in the present specification will be described below.
An operation mode of the DC/DC converter 11 in a case where a clock signal CLKIN input to the clock signal input section 113 is in the Low state is referred to as a “discharge mode”.
In the discharge mode, the DC/DC converter 11 allows a positive electrode of the booster capacitor 12 to be connected to the voltage input section 111. In other words, the booster capacitor 12 is charged with a voltage VIN supplied from the voltage input section 111.
At the same time, the DC/DC converter 11 allows a positive electrode of the output capacitor 13 to be connected to the booster voltage output section 112. In other words, the output capacitor 13 discharges electric power to an arbitrary external device connected to the booster voltage output section 112.
On the other hand, an operation mode of the DC/DC converter 11 in a case where the clock signal CLKIN input to the clock signal input section 113 is in the High state is referred to as a “charge mode”.
In the charge mode, the DC/DC converter 11 allows a negative electrode of the booster capacitor 12 to be connected to the voltage input section 111. Also, the DC/DC converter 11 allows the positive electrode of the booster capacitor 12 to be connected to the positive electrode of the booster voltage output section 112. At this time, the booster capacitor 12 has been already charged with the voltage of the voltage input section 111 in the discharge mode. Thus, the voltage input section 111 and the booster capacitor 12 that are serially connected charge the output capacitor 13. In other words, electrical charges in the booster capacitor 12 are shared with the output capacitor 13. As a result, the output capacitor 13 is charged with a voltage which is twice as much as the voltage of the voltage input section 111.
The DC/DC converter 11 which performs an operation in an opposite phase to that in the example shown in FIG. 2 can be easily realized by basically inverting the logic in this circuit. Furthermore, a booster ratio, the number of the used various capacitors and the type and total number of the operation modes can be changed in many ways. Description of these changes can be easily inferred and thus, is omitted.
Next, an operation of the feedback circuit section 20 shown in FIG. 2 will be described.
First, the voltage dividing circuit section 24 divides a voltage VOUT of the booster voltage output section 112 and outputs the divided voltage from the voltage dividing node 240. The voltage output from the voltage dividing node 240 is hereinafter referred to as a “feedback voltage VFB”. At this time, the booster voltage output section 112, the second fixed resistor (R2) 242, the voltage dividing node 240, the first fixed resistor (R1) 241 and the ground 249 are connected in series. The feedback voltage VFB is a voltage between both nodes of the first fixed resistor 241. Therefore, the feedback voltage VFB can be represented by the following Equation (1).VFB=VOUT×R1/(R1+R2)  <Equation (1)>
A coefficient R1/(R1+R2) in the right side of the Equation (1) is hereinafter referred to as a “voltage dividing ratio”.
Next, the feedback voltage VFB is input to an inverted side input section of the comparator 210 in the comparison circuit section 21. The comparator 210 compares the feedback voltage VFB with a reference voltage VREF of the reference voltage source 220 connected to the non-inverted side input section of the comparator 210. The comparison circuit section 21 outputs a result of the comparison between the voltages as a feedback signal EN. For example, the feedback signal EN is in the Low state in a case where the feedback voltage VFB is higher than the reference voltage VREF (VFB>VREF). In the other cases, the feedback signal EN is in the High state.
The feedback signal EN is supplied to the logic circuit section 30. An external clock signal CLK is further supplied from the external clock signal input section 31 to the logic circuit section 30. When the feedback signal EN is in the High state and the external clock signal CLK is in the High state, the clock signal CLKIN output from the logic circuit section 30 is in the High state (charge mode). Electrical charges in the booster capacitor 12 are supplied to the output capacitor 13. As a result, the booster operation of the charge pump 10 is performed.
When the external clock signal CLK is in the Low state or the feedback signal EN is in the Low state, the clock signal CLKIN output from the logic circuit section 30 is in the Low state (discharge mode). The booster operation is turned OFF, and the output capacitor is discharged. Also, the booster capacitor 12 is charged with the input voltage VIN supplied from the voltage input section 111, in preparation for the next booster operation.
The feedback signal EN is output from the comparator 210 which compares the feedback voltage VFB with the reference voltage VREF. In other words, timing when the feedback signal EN is switched is determined by the operation of the comparator 210. Specifically, the feedback signal EN is switched when a relationship represented by the following Equation (2) is satisfied. In other words, the comparator 210 operates so as to keep a relationship represented by the following Equation (3).VREF=VFB=VOUT×R1/(R1+R2)  <Equation 2>VOUT=VREF×(1+R2/R1)  <Equation 3>
The value of the right side of the Equation (3) is hereinafter referred to as a “set voltage”.
In a case where the output voltage VOUT is higher than the above-mentioned set voltage, the feedback signal EN is in the Low state. When the feedback signal EN is in the Low state, the clock signal CLKIN input to the DC/DC converter 11 is in the Low state, irrespective of the external clock signal CLK. As a result, the booster operation is stopped. At this time, in the case shown in FIG. 2, the booster capacitor 12 is charged.
In a case where the output voltage VOUT is lower than the above-mentioned set voltage, the feedback signal EN is in the High state. Furthermore, when the external clock signal CLK which operates the booster circuit is in the High state, the booster operation is performed. In other words, charging and discharging of each capacitor are repeated.
In the case shown in FIG. 2, since a logical operation of the external clock signal CLK and the feedback signal EN is performed, the DC/DC converter 11 does not necessarily operate in synchronization with the external clock signal CLK. For example, let us consider a case where a period during which the feedback signal EN is in the High state is a half of a period during which the external clock signal CLK is in the High state. In this case, the discharge operation of the booster capacitor 12 is performed for a half of the period during which the external clock signal CLK is in the High state.
However, a current at the time when electrical charges in the booster capacitor 12 are discharged to the output capacitor 13 may not correspond to a current at the time when electrical charges in the output capacitor 13 are discharged to the external load. Furthermore, since a reaction speed of the feedback circuit section 20 including the comparator 210 is limited, a waveform of the output voltage VOUT includes ripple noise which fluctuates across the above-mentioned set voltage.
FIG. 3 is a waveform diagram for explaining the waveform of the output voltage VOUT including the ripple noise and influence of the ripple noise on a display waveform of a display device. In FIG. 3, the horizontal axis represents time and the vertical axis represents voltage. The set voltage is indicated by a broken line. The details will be described later.
Japanese Patent Publication JP-2005-278383A discloses a power supply circuit. In the power supply circuit, a comparator makes a comparison between a reference voltage and a voltage depending on an output of a charge pump which performs the booster operation in accordance with a clock signal. A pulse of the clock signal is skipped by the output of the comparator at the time when the voltage exceeds the reference voltage to stop the booster operation. The skip of the pulse of the clock signal is stopped by the output of the comparator at the time when the voltage falls below the reference voltage to restart the booster operation, thereby outputting a regulated voltage from the charge pump. Here, a speed of the comparator is controlled so as to be high from the time when the voltage depending on the output of the charge pump exceeds the reference voltage to the time when the output of the comparator is inverted. Also, the speed of the comparator is controlled so as to be low from the time when the voltage depending on the output of the charge pump falls below the reference voltage to the time when the output of the comparator is inverted.
The inventor of the present application has recognized the following points.
As mentioned above, the output voltage VOUT of the feedback-control-type booster circuit has the ripple waveform. A negative effect of this phenomenon on an actual display panel will be described below.
FIG. 4 is a circuit diagram showing a liquid crystal display panel system using the booster circuit shown in FIG. 2. The liquid crystal display panel system in FIG. 4 has an LCD (Liquid Crystal Display) driver and a liquid crystal display panel. As shown in FIG. 4, the voltage output from the booster circuit is used as power source for the LCD driver in the liquid crystal display panel system. The LCD driver has amplifying buffers for driving a predetermined voltage to the liquid crystal display panel.
The liquid crystal display panel shown in FIG. 4 has a plurality of pixels. Each of the plurality of pixels has an FET (Field Effect Transistor). Scan signal lines G1, G2, . . . used for transmitting a gate control signal are connected to gates of the plurality of FETs, respectively. Data lines S1, S2, . . . for transmitting a source line signal are connected to sources of the plurality of FETs, respectively. Here, the gate control signal is used for driving each pixel of the liquid crystal display panel. The source line signal is used for applying a voltage corresponding to data displayed at each pixel of the liquid crystal display panel.
The (A) part of FIG. 3 is a waveform diagram showing the gate control signals of the scan signal lines G1, G2 and G3, the source line signal of the data line S1, and the output voltage VOUT of the booster circuit for driving the liquid crystal display panel. Here, the gate control signal is in synchronization with the source line signal. The (B) part of FIG. 3 is a magnified diagram of a part of the (A) part, which illustrates in more detail the gate control signal of the scan signal line G1, the source line signal of the data line S1, and the output voltage VOUT of the booster circuit.
FIG. 5 is a diagram for explaining an influence of the noise of the driver power source on the liquid crystal display device. The plurality of scan signal lines G1, G2, . . . are activated one by one in order. When a scan signal line is activated, all pixels connected to the activated scan signal lines are activated. An analog value output from the source driver is written to the activated pixels through the data lines.
The transistor of each pixel is turned ON in synchronization with the gate control signal. When the transistor of each pixel is turned ON, a load capacitor of the each pixel is charged. Thus, a load current of each pixel is in synchronization with the gate control signal. However, electrical charges charged to each pixel vary depending on an image displayed at this time. That is to say, the load current varies for each display line and the amount of charge consumption is irregular.
Therefore, a timing of starting the booster operation for boosting the output voltage VOUT that has been decreased due to the load driving also is irregular and, in many cases, not in synchronization with the display operation. The waveform shown in FIG. 3 is an example. The rising waveform is steep. In order to increase the electrical charges stored in the booster capacitor 12, the negative electrode terminal is switched to the voltage input section 111. Since the switching operation is performed for sharing the electrical charges with the booster voltage output section 112, the voltage waveform becomes steep in the AC manner. In addition, a low impedance of a booster SW also contributes to the steep voltage waveform.
On the other hand, the discharging is averagely performed through the output capacitor 13 which operates as a bypass capacitor. Furthermore, the discharging is performed with a current limited by an amplifier output impedance and the liquid crystal display panel load. The discharging charges are less than that in the booster capacitor. For these reasons, the waveform is averagely smooth.
Due to the above-described asynchronous and steep rising, a steep rising ripple noise occurs in the output voltage VOUT if the booster operation based on the discharging of the booster capacitor 12 starts immediately before switching of the scan signal lines. Moreover, the noise is transmitted to the output of the amplifier that uses the output voltage VOUT output from the booster voltage output section 112 as the power source. Especially when this occurs immediately before completion of scanning as shown in FIG. 3, it is difficult to return the voltage to a predetermined voltage by the amplifier, which results in that a voltage shifted from the predetermined voltage is applied to the source line.
FIG. 5 shows a state where the power source noise affects the pixels of the liquid crystal display panel. In fact, not all the power source noise is applied to the driver outputs (S1, S2, . . . ), and a part thereof depending on power-source-noise-removal-ratio of the amplifier appears as the output. Accordingly, the noise applied to the source line is generally smaller than the actual power source noise by about one digit.
However, the higher-definition and higher-contrast liquid crystal display panel in recent years requires further precision for the LCD driver amplifier. Therefore, the influence of the above-mentioned noise cannot be ignored. Specifically, the above-mentioned noise is irregularly applied and hence the voltage is irregularly shifted from the predetermined voltage, which causes line flicker in screen during display.